1. Field of the Invention
The present invention relates to a clock recovery circuit which is used for, e.g., high-speed data communication.
2. Description of the Related Art
In a data communication system, in order to perform serial transmission between communication devices having clock signal sources different from each other, a communication device on a reception side requires clocks with the same frequency as that of a communication device on a transmission side. In this case, the reception side generates a sampling clock synchronized with reception data so as not to generate a frequency offset, and samples the reception data by using this clock, thereby acquiring reproduction data.
There are various kinds of clock recovery circuit which generate a sampling clock synchronized with reception data, and a clock recovery circuit using a multiphase clock is one of such circuits. In this mode, the multiphase clocks having n phases are used, and a phase comparator compares a leading (or trailing) edge of reception data with an edge of a sampling clock selected from the n-phase clocks in phase until an optimum clock is reached, thereby selecting the optimum clock from the n-phase clocks.
However, the prior art clock recovery circuit cannot correct a phase of the sampling clock to an ideal position immediately even though it tries to correct the phase of the sampling clock to the ideal position when a period with no transition of a value of the reception data is long, which leads to a problem of many reading errors of the reception data.
Therefore, there has been demanded a clock recovery circuit which produces no reading error even if the period with no transition of a value of reception data is long, in which a clock recovery system stably operates in a balanced state, and which can realize an ideal clock recovery system having a high tracking property when a large correction is required.